Hybrid Interconnect Scheme and Methods for Forming the Same

ABSTRACT

A device includes a first low-k dielectric layer, and a copper-containing via in the first low-k dielectric layer. The device further includes a second low-k dielectric layer over the first low-k dielectric layer, and an aluminum-containing metal line over and electrically coupled to the copper-containing via. The aluminum-containing metal line is in the second low-k dielectric layer.

PRIORITY CLAIM AND CROSS-REFERENCE

This application is a continuation of U.S. patent application Ser. No. 14/229,306, entitled “Hybrid Interconnect Scheme and Methods for Forming the Same,” filed Mar. 28, 2014, which application is a divisional of U.S. patent application Ser. No. 13/554,817, entitled “Hybrid Interconnect Scheme Including Aluminum Metal Line in Low-K Dielectric,” filed on Jul. 20, 2012, now U.S. Pat. No. 8,710,660, which applications are incorporated herein by reference.

BACKGROUND

Modern integrated circuits are made up of transistors, capacitors, and other devices that are formed on semiconductor substrates. On a substrate, these devices are initially isolated from one another but are later interconnected together to form functional circuits. Typical interconnect structures include lateral interconnections, such as metal lines (wirings), and vertical interconnects, such as vias and contacts. The quality of the interconnect structure affects the performance and the reliability of the fabricated circuit. Interconnections are increasingly determining the limits of performance and density of modern integrated circuits.

The interconnect structures may include tungsten plugs and aluminum lines. In newer generations of the integrated circuits, dual damascene structures, which include copper lines and vias formed using dual damascene processes, were also used to form the interconnect structures.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIGS. 1 through 11 are cross-sectional views of intermediate stages in the manufacturing of an interconnect structure in accordance with some exemplary embodiments.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are illustrative, and do not limit the scope of the disclosure.

An interconnect structure and the method of forming the same are provided in accordance with various exemplary embodiments. The intermediate stages of forming the interconnect structure are illustrated. The variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.

FIG. 1 illustrates wafer 100, which includes semiconductor substrate 10. Semiconductor substrate 10 may be formed of silicon, germanium, silicon germanium, III-V compound semiconductor, or the like. Active and passive devices 12, such as transistors, capacitors, resistors, and the like, may be formed adjacent to the top surface of semiconductor substrate 10.

FIG. 1 also illustrates the formation of Inter-Layer Dielectric (ILD) 14 and contact plugs 16. ILD 14 may be formed using Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), Tetraethyl Orthosilicate (TEOS) oxide, or the like. Contact plugs 16, which may comprise tungsten, may be formed in ILD 14, and connected to devices 12. Dielectric layer 20 is formed over ILD 14. Dielectric layer 20 is alternatively referred to as an Inter-Metal Dielectric (IMD) layer. In some embodiments, IMD layer 20 comprises a low-k dielectric material, which has a dielectric constant (k value) lower than 3.9. The k value of IMD layer 20 may also be lower than about 3.0, or lower than about 2.5.

Metal lines 22 are formed in IMD layer 20. Throughout the description, the metal lines in an IMD layer are collectively referred to as a metal layer. Accordingly, metal lines 22 are in bottom metal layer M1. Metal lines 22 may be formed using a single damascene process, which is similar to the process shown in FIGS. 1 and 2. In some embodiments, metal lines 22 are formed by depositing and etching an aluminum-containing layer (such as AlCu), and patterning the aluminum-containing layer. In alternative embodiments, metal lines 22 are formed using a single damascene process, and hence may include barrier layer 22A, and copper-containing layer 22B over barrier layer 22A. Barrier layer 22A may include titanium, titanium nitride, tantalum, tantalum nitride, or other alternatives. Metal lines 22 may have thickness T1 between about 10 nm and about 50 nm, and width W1 between about 8 nm and about 30 nm, for example.

Referring again to FIG. 1, IMD layer 24 is formed over IMD 20. In some embodiments, IMD layer 24 has a dielectric constant (k value) lower than about 3.5, hence is referred to as low-k IMD layer 24 throughout the description. The k value of low-k IMD layer 24 may also be lower than about 2.8. In some embodiments, low-k IMD layer 24 includes oxygen, silicon, nitrogen, and the like. The exemplary materials include carbon-containing materials, organo-silicate glass, porogen-containing materials, and the like. Pores may be formed in low-k IMD layer 24 for lowering its k value. Low-k IMD layer 24 may be deposited using a CVD method such as Plasma Enhanced CVD (PECVD), although other deposition methods such as Low Pressure CVD (LPCVD), Atomic Layer CVD (ALCVD), and spin-on can also be used.

A single damascene process is shown in FIGS. 1 and 2. In FIG. 1, via openings 26 are formed in low-k IMD layer 24 by etching IMD layer 24. In some embodiments, an etch stop layer (not shown) is formed under IMD layer 24 and over IMD layer 20, wherein the etch stop layer may include a nitride, a silicon and carbon based dielectric, a carbon-doped oxide, or the like.

FIG. 2 illustrates the filling of via openings 26 in order to form vias 32. In some embodiments, diffusion barrier layer 28 is formed first, which is a blanket layer including portions in via openings 26 and portions over IMD layer 24. A seed layer (not shown, merged with copper-containing material 30) is then formed over diffusion barrier layer 28, followed by a plating step to form copper-containing material 30, until the top surface of copper-containing material 30 is higher than the top surface of low-k IMD layer 24. Diffusion barrier layer 28 may include titanium, titanium nitride, tantalum, tantalum nitride, or other alternatives. Copper-containing material 30 may comprise over 90 atomic percent, over 95 atomic percent, or over 99 atomic percent copper in some exemplary embodiments. Next, a Chemical Mechanical Polish (CMP) is performed to remove the excess portions of copper-containing material 30 and diffusion barrier layer 28 that are over low-k IMD layer 24, leaving vias 32 in IMD layer 24.

Next, as shown in FIG. 3, ESL 34, which may be formed of silicon nitride, silicon carbide, or the like, is formed over IMD layer 24 and vias 32. In alternative embodiments, no ESL 34 is formed. ESL 34 may have thickness T8 between about 2 nm and about 20 nm, for example. Next, referring to FIG. 4, a conductive layer stack, which includes conductive barrier 36 and aluminum-containing layer 38, is formed in a deposition-and-patterning process. In some embodiments, conductive barrier layer 40 is further formed on aluminum-containing layer 38. In alternative embodiments, conductive barrier layer 40 is not formed. Conductive barrier layers 36 and 40 (if any) may include titanium, titanium nitride, tantalum, tantalum nitride, or other alternatives. Aluminum-containing layer 38 may comprise over 90 atomic percent, over 95 atomic percent, or over 99 atomic percent aluminum in some exemplary embodiments. The stacked layers are then patterned to form metal lines 42, which are electrically coupled to (and may be in contact with) the respective underlying vias 32. Since layers 36, 38, and 40 are patterned using a same lithography mask, layers 36, 38, and 40 are co-terminus, with the corresponding edges of layers 36, 38, and 40 aligned to each other. Throughout the description, metal lines 42 are collectively referred to metal layer M2. In the patterning step, ESL 34 and/or conductive barrier 36 may be used as etch stop layers. Throughout the description, vias 32 and the overlying metal lines 42, whose formation is a hybrid process including a single damascene process and a deposition-and-patterning process, are in combination referred to as a hybrid structure. Conductive barrier 36 may have thickness T2 between about 1 nm and about 20 nm. Aluminum-containing layer 38 may have thickness T3 between about 10 nm and about 50 nm. Conductive barrier layer 40 may have thickness T4 between about 1 nm and about 20 nm. Metal lines 42 may have width W2 between about 8 nm and about 30 nm, for example.

FIG. 5 illustrates the formation of dielectric barrier 44, which comprises sidewall portions on the sidewalls of metal lines 42, top portions overlapping metal lines 42, and lower portions on ESL 34. Dielectric barrier 44 may have thickness T5 between about 1 nm and about 20 nm. In the embodiments wherein no conductive barrier layer 40 is formed, the top portions of dielectric barrier 44 contact the top surfaces of aluminum-containing layers 38 in metal lines 42. Otherwise, if conductive barrier layer 40 is formed, the top portions of dielectric barrier 44 contact the top surfaces of conductive barrier layer 40 in metal lines 42. Dielectric barrier 44 may be formed of AlOx, AlNx, SiCN, SiN, or the like, wherein “x” has a value between 0 and 1. Dielectric barrier 44 may be formed using, for example, Atomic Layer Deposition (ALD).

FIG. 6 illustrates the formation of IMD layer 46. The material of IMD layer 46 may be selected from the same group of available materials for forming IMD layer 24 and/or IMD layer 20. In some embodiments, IMD layer 46 is formed using a Spin-On Dielectric (SOD), which has a low k value. In alternative embodiments, IMD layer 46 may be formed using a Chemical Vapor Deposition (CVD) method such as PECVD, LPCVD, ALCVD, or the like. As a result of the CVD method, void 48 may be formed in IMD layer 46 and between neighboring void 48 may reduce the effective k value of IM layer 46, and reduce the parasitic capacitance between metal lines 42. In the embodiments wherein the CVD method is used for forming IMD layer 46, a CMP or grinding may be performed to level the top surface of IMD layer 46. In the embodiments wherein the SOD is used for forming IMD layer 46, the CMP or the grinding step may be performed, or may be omitted. In The top surface of IMD layer 46 is higher than the top surface of metal lines 42 and the top portions of dielectric barrier layer 44.

In FIG. 7, vias 50 are formed using a single damascene process, wherein the formation may be essentially the same as shown in FIGS. 1 and 5. Vias 50 are formed in IMD layer 46, and are electrically coupled to underlying metal lines 42. Vias 50 penetrate through dielectric layer 44 to electrically couple to metal lines 42. In a subsequent step, as shown in FIG. 8, metal lines 52 are formed, wherein the formation process may be essentially the same as the formation of metal lines 42. Dielectric barrier layer 47 may then be formed, for example, with a similar material and a similar thickness as dielectric barrier layer 44. Metal lines 52 are collectively referred to as metal layer M3. Each of metal lines 52 includes conductive barrier layer 54 and aluminum-containing layer 56 over conductive barrier layer 54. Aluminum-containing layer 56 may have thickness T6 between about 10 nm and about 50 nm, and width W3 between about 8 nm and about 30 nm, for example. Conductive barrier layer 54 and aluminum-containing layer 56 may be formed using essentially the same method and same materials as conductive barrier layer 36 and aluminum-containing layer 38, respectively. In the illustrated embodiments, no ESL is formed over IMD layer 46 and underlying dielectric layer 47, although an ESL (not shown) may be formed, wherein the ESL may be formed using similar material and similar thickness as ESL 34. Furthermore, no conductive barrier layer is formed in the illustrated embodiments, although a conductive barrier layer similar to conductive barrier layer 40 may also be formed over and adjoining aluminum-containing layer 56.

FIGS. 9 and 10 illustrate the formation of the rest of low-k dielectric layers up to the top metal layer Mtop (please refer to FIG. 10), which is the topmost metal layer that is formed in a low-k dielectric layer. The sign “top” in the term “Mtop” represents an integer, which may be any integer between about 3 and about 10, for example. Accordingly, the metal layer under metal layer Mtop is referred to as metal layer Mtop-1. In some embodiments, each of metal layers M2 through Mtop and the respective underlying vias has the hybrid structure. The hybrid structure includes vias formed using a single damascene process, and aluminum-containing metal lines over and contacting the vias, with the aluminum-containing metal lines formed using deposition and patterning, rather than the single damascene or the dual damascene process. In alternative embodiments, each of lower metal layers M2 through Mn (not shown) and the respective underlying vias forms the hybrid structures, while each of upper metal layers M(n+1) (not shown) through Mtop is formed using dual damascene processes, wherein integer n may be any integer between, and including, 2 and (top−1). For example, FIGS. 9 and 10 schematically illustrates a dual damascene process for forming the upper metal layers.

Referring to FIG. 9, IMD layer 58, which is a low-k dielectric layer, is formed. Next, via openings 60 and trenches 62 are formed in IMD layer 58 using etching processes. Next, as shown in FIG. 10, via openings 60 and trenches 62 are filled, followed by a CMP process. The filling material may include conductive barrier layer 64 and conductive material 66 over conductive barrier layer 64. Conductive barrier layer 64 may be formed of titanium, titanium nitride, tantalum, tantalum nitride, or the like. Thickness T7 of conductive barrier layer 64 may be between about 5 nm and about 50 nm, for example. Conductive material 66 may comprise copper or a copper alloy. As a result of the filling step and the CMP step, vias 68 and metal lines 70 are formed in via openings 60 and trenches 62, respectively. Metal lines 70 may have thickness T9 between about 100 nm and about 5,000 nm, and width W4 between about 50 nm and about 5,000 nm, for example.

FIG. 11 illustrate the formation of non-low-k dielectric layers 72, which may be formed of silicon oxide, silicon nitride, un-doped silicate glass, or the like. Metal routing (not shown) may be formed in non-low-k dielectric layers 72, and electrically coupled to the underlying metal layers M1 through Mtop.

In the embodiments, the metal lines in the interconnect structure may include aluminum-containing metal lines. Aluminum-containing lines that are formed mainly of aluminum, when having line widths between about 40 nm and about 50 nm or smaller, may have a line resistivity smaller than that of copper lines having the same widths. Furthermore, with the further reduction of the line widths of the aluminum lines, the difference between the line resistivity of the aluminum lines and the line resistivity of the copper lines (having the same widths), is increasingly higher with the increasingly reduction of the line widths. Accordingly, adopting aluminum lines when the line widths are small may result in reduced line resistivity and reduced RC delay. On the other hand, when aluminum lines are formed through deposition and patterning, the underlying vias are formed using single damascene processes, rather than dual damascene processes. Accordingly, the gap filling into the via openings is easier than the gap filling of both the trenches and the vias openings in dual damascene processes.

Furthermore, the upper metal layers such as metal layer Mtop may have greater line width than the underlying metal layers. Accordingly, the upper metal layers may adopt dual damascene processes, with the metal lines in the upper metal layers comprising copper lines, while the lower metal layers may adopt the hybrid structures. Accordingly, the line resistivity values of the upper metal layers and the lower metal layers are optimized.

In accordance with embodiments, a device includes a first low-k dielectric layer, and a copper-containing via in the first low-k dielectric layer. The device further includes a second low-k dielectric layer over the first low-k dielectric layer, and an aluminum-containing metal line over and electrically coupled to the copper-containing via. The aluminum-containing metal line is in the second low-k dielectric layer.

In accordance with other embodiments, a device includes a first low-k dielectric layer, a first copper-containing via in the first low-k dielectric layer, a second low-k dielectric layer over the first low-k dielectric layer, and a conductive line in the second low-k dielectric layer and electrically coupled to the first copper-containing via. The conductive line includes a conductive barrier layer, and an aluminum-containing metal line over the conductive barrier layer. A dielectric barrier layer includes first portions on sidewalls of the aluminum-containing metal line, a second portion overlapping the aluminum-containing metal line, and a third portion underlying the second low-k dielectric layer.

In accordance with yet other embodiments, a method includes forming a first via in a first low-k dielectric layer using a single damascene process, depositing an aluminum-containing layer over the first via, and patterning the aluminum-containing layer to form an aluminum-containing line. The aluminum-containing line is electrically coupled to the first via. A second low-k dielectric layer is formed over the first low-k dielectric layer, wherein the aluminum-containing line is in the second low-k dielectric layer.

Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure. 

What is claimed is:
 1. A method comprising: forming a copper-containing conductive feature in a first low-k dielectric layer; performing a deposition-and-patterning step to form an aluminum-containing metal line over and electrically coupled to the copper-containing conductive feature; and forming a dual damascene structure over and electrically coupled to the aluminum-containing metal line, wherein the dual damascene structure comprises a copper-containing line and a copper-containing via underlying the copper-containing line.
 2. The method of claim 1 further comprising forming a second low-k dielectric layer covering the aluminum-containing metal line, wherein the second low-k dielectric layer further comprises portions on opposite sides of, and at a same level as, the aluminum-containing metal line.
 3. The method of claim 2 further comprising forming a via in a top portion of the second low-k dielectric layer using a single damascene process, wherein the via has a top surface coplanar with a top surface of the second low-k dielectric layer.
 4. The method of claim 1, wherein the forming the copper-containing conductive feature is a part of a single damascene process.
 5. The method of claim 1 further comprising forming a metal line comprising aluminum and copper, with the copper-containing conductive feature overlying and in contact with the metal line.
 6. The method of claim 1 further comprising: forming a dielectric barrier layer comprising: a sidewall portion contacting a sidewall of the aluminum-containing metal line; and a top portion overlapping the aluminum-containing metal line, wherein the copper-containing via in the dual damascene structure penetrates through the top portion of the dielectric barrier layer.
 7. The method of claim 6 further comprising forming a top diffusion barrier layer over and contacting the aluminum-containing metal line, wherein the top diffusion barrier layer and the aluminum-containing metal line are co-terminus, and the dual damascene structure has a bottom surface contacting a top surface of the top diffusion barrier layer.
 8. The method of claim 1 further comprising a bottom diffusion barrier layer underlying and contacting the aluminum-containing metal line, wherein the bottom diffusion barrier layer and the aluminum-containing metal line are co-terminus.
 9. A method comprising: forming a first via in a first low-k dielectric layer using a single damascene process; depositing an etch stop layer over the first low-k dielectric layer and the first via; depositing a metal layer over and contacting the etch stop layer and the first via; patterning the metal layer to form a first metal line, wherein the first metal line extends into the etch stop layer to contact the first via; forming a dielectric barrier layer comprising sidewall portions on sidewalls of the first metal line, and a top portion over the first metal line; forming a second low-k dielectric layer over the dielectric barrier layer, wherein the second low-k dielectric layer comprises a first portion overlapping the first metal line, and a second portion at a same level as the first metal line; and forming a second via in the second low-k dielectric layer using a damascene process, wherein the second via penetrates through the top portion of the dielectric barrier layer to electrically couple to the first metal line.
 10. The method of claim 9, wherein the second via is formed using a single damascene process, and a top surface of the second via is coplanar with a top surface of the second low-k dielectric layer.
 11. The method of claim 9, wherein the second via is formed using a dual damascene process, and the dual damascene process further results in a second metal line over and joined to the second via, and a top surface of the second metal line is coplanar with a top surface of the second low-k dielectric layer.
 12. The method of claim 9, wherein the depositing the metal layer comprises: depositing a diffusion barrier layer, with the diffusion barrier layer comprising titanium or tantalum; and depositing an aluminum-containing layer over the diffusion barrier layer.
 13. The method of claim 9, wherein the depositing the metal layer comprises: depositing an aluminum-containing layer over and in contact with the first via and the etch stop layer; and depositing a diffusion barrier layer over the aluminum-containing layer, with the diffusion barrier layer comprising titanium or tantalum.
 14. The method of claim 13, wherein the second via is in physical contact with a top surface of the diffusion barrier layer.
 15. A method comprising: forming a plurality of hybrid structures, wherein upper ones of the plurality of hybrid structures are overlying and electrically coupling to respective lower ones of the plurality of hybrid structures, and each of the plurality of hybrid structures is formed by: a single damascene process to form a via; and a deposition-and-patterning process to form a metal line over and contacting the via; and forming a plurality of dual damascene structures overlying and electrically coupling to the plurality of hybrid structures, wherein upper ones of the plurality of dual damascene structures are overlying and electrically coupling to respective lower ones of the plurality of dual damascene structures.
 16. The method of claim 15, wherein the metal line comprises aluminum, and the via comprises copper.
 17. The method of claim 15, wherein the single damascene process comprises: forming a low-k dielectric layer comprising a first portion overlapping the metal line in an underlying hybrid structure, and a second portion at a same level as the metal line in the underlying hybrid structure; forming an opening in the first portion of the low-k dielectric layer; filling a conductive material into the opening; and removing portions of the conductive material over the low-k dielectric layer, with a remaining portion of the conductive material in the opening forming the via.
 18. The method of claim 15, wherein forming one of the hybrid structures further comprises: forming a dielectric barrier layer on a sidewall and a top surface of the metal line.
 19. The method of claim 15, wherein first widths of the metal lines in the plurality of hybrid structures are smaller than second widths of additional metal lines in the plurality of dual damascene structures.
 20. The method of claim 15, wherein a bottommost one of the plurality of hybrid structures is over and contacting line comprising aluminum and copper. 